1. Field of the Invention
The present invention relates to a semiconductor memory having dynamic memory cells that require a refresh operation and a method for operating the same.
2. Description of the Related Art
Recently, a semiconductor memory referred to as a pseudo SRAM has been drawing attention. The pseudo SRAM has DRAM memory cells, operating as an SRAM that automatically executes an internal refresh operation of the memory cells. Because the dynamic memory cell has a small size, the bit cost is low, and accordingly, it is possible to develop the pseudo SRAM having a large capacity.
However, since the pseudo SRAM stores data with charges accumulated in a capacitor of the memory cell, data might be lost due to charge leakage and so on. To avoid this, the pseudo SRAM is required to perform a refresh operation for each predetermined period. The refresh operation reads out data stored in the memory cell to a bit line, amplifies the data on the bit line, and rewrites the data into the memory cell.
A refresh request for performing the refresh operation is generated regardless of an external access request. For this reason, the refresh operation may conflict with an access operation. The pseudo SRAM is required to hide the refresh operation against an external system even when the conflict occurs, in order to have an SRAM interface. Recently, in order to hide the refresh operation, a semiconductor memory has been proposed in which an error correction code as well as write data is stored (e.g., see Japanese Unexamined Patent Application Publication No. 2003-51186). The semiconductor memory uses the error correction code to regenerate read data without reading out data from a memory block under the refresh operation. In addition, a read request does not conflict with a refresh request, so that it is not necessary that the refresh operation time be included in a read cycle time. As a result, the read cycle time can be equivalent to that of the SRAM.
Further, since the pseudo SRAM requires the refresh operation, its power consumption during a standby period is large, as compared with an SRAM whose memory cell includes a latch. The power consumed during the standby period has a DC component and an AC component. The DC component, which is a leak component, refers to an off-current of the transistor and a current intentionally being flowed due to the existence of an internal circuit (in particular, power supply circuit). In addition to this, the DC component depends on how the semiconductor is processed and how the circuit is constructed, so it is beyond dispute that there is a difference between a pseudo SRAM and an SRAM.
The AC component of the current consumed during the standby period of the pseudo SRAM is mainly a current from the refresh operation. For this reason, a reduction of the refresh operation current is effective for reducing the AC component. Recently, in order to reduce the refresh operation current, a semiconductor memory has been proposed in which write data together with an error correction code are stored. The semiconductor memory substantially improves data retention characteristics of the memory cell with the error correction code, and extends a refresh interval to thus reduce the refresh operation current (e.g., see Japanese Unexamined Patent Application Publication No. 5-41084, Japanese Unexamined Patent Application Publication No. 2002-56671, and Japanese Unexamined Patent Application Publication No. 2003-59290).
However, in the error correction method used in the above-mentioned conventional pseudo SRAM, it is possible to perform only either reduction of a read cycle time or reduction of a standby current. Specifically, the read cycle time (AC characteristics) may be equivalent to the SRAM, while the standby current (DC characteristics) may not be equivalent to the SRAM. Alternatively, the standby current may be equivalent to the SRAM, while the read cycle time may not be equivalent to the SRAM. In other words, the pseudo SRAM being completely compatible to the SRAM is not realized yet. As a result, it is difficult to operate the system in the manner where the SRAM embedded in the system may be simply replaced with the pseudo SRAM, for example, for the sake of cost reduction.